In recent years, in order to cope with an increase in an amount of heat generation along with enhancement in performance of a semiconductor device, high thermal conduction of a central processing unit (CPU) package structure is realized by using solder serving as a thermal interface material (TIM) between a large scale integration (LSI) and a heat spreader.
For example, a composite material including a thermally conductive metal and silicone particles in the above-described thermally conductive metal (for example, refer to Japanese National Publication of International Patent Application No. 2010-539683), a complex including a homogeneously dispersed material of an indium metal and at least one type of ceramic material and having a thermal conductivity of at least 80 W/mK (for example, refer to Japanese Laid-open Patent Publication No. 2009-161850), and a TIM serving as a phase change portion composed of at least one type of low-melting point metal selected from the group consisting of Ga, In, and Sn or an alloy containing the above-described at least one type of low-melting point metal (for example, refer to Japanese Laid-open Patent Publication No. 2007-335742) have been proposed as the above-described TIM.
In general, it is known that voids are generated at a junction interface of soldering. In the case where the TIM is used, voids lead to reduction in the cooling efficiency and high-temperature irregularity of a device and, therefore, a junction with reduced voids is desired.
However, with respect to the thermal interface materials (TIMs) in the related art including the above-described technologies which have been proposed already, a junction with reduced voids has not been realized because removal of generated voids from the junction surface is difficult.